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DS1992/DS1993 1kb/4kb Memory iButton
www.iButton.com
SPECIAL FEATURES
4096 bits of Read/Write Nonvolatile Memory (DS1993) 1024 bits of Read/Write Nonvolatile Memory (DS1992) 256-bit Scratchpad Ensures Integrity of Data Transfer Memory Partitioned into 256-bit Pages for Packetizing Data Data Integrity Assured with Strict Read/Write Protocols Operating Temperature Range from -40C to +70C Over 10 years of data retention

Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed onto its Rim Presence Detector Acknowledges When Reader First Applies Voltage Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class I, Division 1, Group A, B, C and D Locations
F5 MICROCAN
5.89 0.36 0.51
(c) 1993
COMMON iButton FEATURES
Unique, Factory-Lasered and Tested 64-bit Registration Number (8-bit Family Code + 48-bit Serial Number + 8-bit CRC Tester) Assures Absolute Traceability Because No Two Parts are Alike Multidrop Controller for MicroLAN Digital Identification and Information by Momentary Contact Chip-Based Data Carrier Compactly Stores Information Data Can be Accessed While Affixed to Object Economically Communicates to Bus Master with a Single Digital Signal at 16.3kbps Standard 16mm Diameter and 1-Wire(R) Protocol Ensure Compatibility with iButton(R) Family Button Shape is Self-Aligning with CupShaped Probes Durable Stainless Steel Case Engraved with Registration Number Withstands Harsh Environments
DD
16.25
RR
YYWW REGISTERED
06
17.35
000000FBD804

IO GND
All dimensions shown in millimeters.
ORDERING INFORMATION
DS1992L-F5 DS1993L-F5 F5 MicroCan F5 MicroCan
EXAMPLES OF ACCESSORIES
DS9096P Self-Stick Adhesive Pad DS9101 Multipurpose Clip DS9093RA Mounting Lock Ring DS9093F Snap-In Fob DS9092 iButton Probe
1-Wire and iButton are registered trademarks of Dallas Semiconductor.
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iButton DESCRIPTION
The DS1992/DS1993 memory iButtons (hereafter referred to as DS199_) are rugged read/write data carriers that act as a localized database, easily accessible with minimal hardware. The nonvolatile memory and optional timekeeping capability offer a simple solution to storing and retrieving vital information pertaining to the object to which the iButton is attached. Data is transferred serially through the 1-Wire protocol that requires only a single data lead and a ground return. The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command transfers the data to memory. This process ensures data integrity when modifying the memory. A 48-bit serial number is factory lasered into each DS199_ to provide a guaranteed unique identity that allows for absolute traceability. The durable MicroCan package is highly resistant to environmental hazards such as dirt, moisture, and shock. Its compact coin-shaped profile is self-aligning with mating receptacles, allowing the DS199_ to be easily used by human operators. Accessories permit the DS199_ to be mounted on almost any surface including plastic key fobs, photo-ID badges, and PC boards. Applications include access control, work-in-progress tracking, electronic travelers, storage of calibration constants, and debit tokens.
OPERATION
The DS199_ have three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, and 3) 1024-bit (DS1992) or 4096-bit (DS1993) SRAM. All data is read and written least significant bit first. The memory functions are not available until the ROM function protocol has been established. This protocol is described in the ROM functions flow chart (Figure 9). The master must first provide one of four ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM, or 4) skip ROM. After a ROM function sequence has been successfully executed, the memory functions are accessible and the master can then provide any one of the four memory function commands (Figure 6).
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever the data input is high. The data line provides sufficient power as long as the specified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input, lithium is conserved, and 2) if the lithium is exhausted for any reason, the ROM can still be read normally.
64-bit LASERED ROM
Each DS199_ contain a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 2.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift register bits are initialized to zero. Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all zeros.
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Figure 1. DS199_ BLOCK DIAGRAM
ROM FUNCTION CONTROL PARASITEPOWERED CIRCUITRY
1-WIRE PORT
1-W
64-BIT LASERED ROM
MEMORY FUNCTION CONTROL
256-BIT SCRATCHPAD
SRAM 16 PAGES of 256BITs (1993) 4 PAGES of 256BITs (1992) 3V LITHIUM
Figure 2. 64-BIT LASERED ROM
MSB LSB 8-Bit Family Code (06h)1993 (08h)1992 LSB MSB LSB
8-Bit CRC Code MSB LSB MSB
48-Bit Serial Number
Figure 3. 1-WIRE CRC CODE
Polynomial = X + X + X + 1
8 5 4
1 STAGE
st
2 STAGE
nd
3 STAGE
rd
4 STAGE
th
5 STAGE
th
6 STAGE
th
7 STAGE
th
8 STAGE
th
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
INPUT DATA
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Figure 4a. DS1993 MEMORY MAP
SCRATCHPAD PAGE PAGE 0 PAGE 1 PAGE 2 PAGE 3 PAGE 4 PAGE 5 PAGE 6 PAGE 7 MEMORY PAGE 8 PAGE 9 PAGE 10 PAGE 11 PAGE 12 PAGE 13 PAGE 14 PAGE 15 0000h 0020h 0040h 0060h 0080h 00A0h 00C0h 00E0h 0100h 0120h 0140h 0160h 0180h 01A0h 01C0h 01E0h NOTE: Each page is 32 bytes (256 bits). The hex values represent the starting address for each page or register.
Figure 4b. DS1992 MEMORY MAP
SCRATCHPAD PAGE PAGE 0 PAGE 1 MEMORY PAGE 2 PAGE 3 0040h 0060h 0000h 0020h NOTE: Each page is 32 bytes (256 bits). The hex values represent the starting address for each page or register.
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MEMORY
The memory map in Figure 4 shows a 32-Byte page called the scratchpad, and additional 32-Byte pages called memory. The DS1992 contains pages 0 though 3 that make up the 1024-bit SRAM. The DS1993 contain pages 0 through 15 that make up the 4096-bit SRAM. The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command transfers the data to memory. This process ensures data integrity when modifying the memory.
MEMORY FUNCTION COMMANDS
The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the memory. An example follows the flow chart. Three address registers are provided as shown in Figure 5. The first two registers represent a 16-bit target address (TA1, TA2). The third register is the ending offset/data status byte (E/S). The target address points to a unique Byte location in memory. The first 5 bits of the target address (T4:T0) represent the Byte offset within a page. This Byte offset points to one of 32 possible Byte locations within a given page. For instance, 00000b points to the first Byte of a page where as 11111b would point to the last Byte of a page. The third register (E/S) is a read only register. The first 5 bits (E4: E0) of this register are called the ending offset. The ending offset is a Byte offset within a page (1 of 32 Bytes). Bit 5 (PF) is the partial Byte flag. Bit 6 (OF) is the overflow flag. Bit 7 (AA) is the authorization accepted flag.
Figure 5. ADDRESS REGISTERS
7 TARGET ADDRESS (TA1) TARGET ADDRESS (TA2) ENDING ADDRESS WITH DATA STATUS (E/S) (READ ONLY) T7 T15 AA 6 T6 T14 OF 5 T5 T13 PF 4 T4 T12 E4 3 T3 T11 E3 2 T2 T10 E2 1 T1 T9 E1 0 T0 T8 E0
Write Scratchpad Command [0Fh]
After issuing the write scratchpad command, the user must first provide the 2-Byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4:E0) is the Byte offset at which the host stops writing data. The maximum ending offset is 11111b (31d). If the host attempts to write data past this maximum offset, the overflow flag (OF) is set and the remaining data is ignored. If the user writes an incomplete Byte and an overflow has not occurred, the partial Byte flag (PF) is set.
Read Scratchpad Command [AAh]
This command can be used to verify scratchpad data and target address. After issuing the read scratchpad command, the user can begin reading. The first two Bytes are the target address. The next Byte is the ending offset/data status Byte (E/S) followed by the scratchpad data beginning at the Byte offset (T4: T0). The user can read data until the end of the scratchpad, after which the data read is all logic 1's.
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Copy Scratchpad [55h]
This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the user must provide a 3-byte authorization pattern. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag is set and the copy begins. A logic 0 is transmitted after the data has been copied until the user issues a reset pulse. Any attempt to reset the part is ignored while the copy is in progress. Copy typically takes 30ms. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset is copied to memory, starting at the target address. Anywhere from 1 to 32 Bytes can be copied to memory with this command. Whole Bytes are copied even if only partially written. The AA flag is cleared only by executing a write scratchpad command.
Read Memory [F0h]
The read memory command can be used to read the entire memory. After issuing the command, the user must provide the 2-Byte target address. After the two Bytes, the user reads data beginning from the target address and may continue until the end of memory, at which point logic 1's are read. It is important to realize that the target address registers contains the address provided. The ending offset/data status Byte is unaffected. The hardware of the DS1992/DS1993 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See Application Note 114 for the recommended file structure to be used with the 1-Wire environment.)
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Figure 6. MEMORY FUNCTIONS FLOW CHART
Master TX Memory Function Command 0FH Write Scratchpad ? Y Bus Master TX TA1 (T7:T0) Bus Master TX TA2 (T15:T8) DS199X sets Scratchpad Offset = (T4:T0) and Clears (PF, OF, AA) Master TX Data Byte To Scratchpad Offset DS199X sets (E4:E0) = Scratchpad Offset Bus Master TX Reset ? N Scratchpad Offset = 11111b ? Y Y OF = 1 Bus Master TX Data ? N Y Bus Master TX Reset ? DS199X Increments N Scratchpad Offset ScratchN pad Offset = Y Partial 11111b ? Byte Written ? Y Bus Master N PF = 1 RX "1"s Y N AAH Read Scratchpad ? Y Bus Master RX TA1 (T7:T0) Bus Master RX TA2 (T15:T8) Master RX Ending Offset with Data Status (E/S) DS199X Sets Scratchpad Offset=(T4:T0) Master RX Data Byte From Scratchpad Offset To Figure 6 Second Part
DS199X Increments Scratchpad Offset N
N
Bus Master TX Reset ? Y From Figure 6 Second Part DS199X TX Presence Pulse (See Figure 9)
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Figure 6. MEMORY FUNCTIONS FLOW CHART (Continued)
From Figure 6 First Part
55H Copy Scratchpad ? Y Bus Master TX TA1 (T7:T0) Bus Master TX TA2 (T15:T8) Bus Master TX E/S Byte Authrization Code Match ? Y AA = 1 DS199X TX "1"s DS199X Copies Scratchpad Data To Memory DS199X TX "0"s
N
Y F0H Read Memory ? N
Bus Master TX TA1 (T7:T0) Bus Master TX TA2 (T15:T8) DS199X sets Memory Address = (T15:T0)
N
Master RX Data Byte From Memory Address DS199X Increments Address Counter Y Bus Master TX Reset ? N Memory Address = 21Dh ? Y Bus Master RX "1"s
N N Bus Master TX Reset ? Y
Bus Master TX Reset ? Y
N
To Figure 6 First Part
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MEMORY FUNCTION EXAMPLES
Example: Write two data Bytes to memory locations 0026h and 0027h (the seventh and eighth Bytes of page 1). Read entire memory. MASTER MODE TX RX TX TX TX TX TX TX RX TX TX RX RX RX RX TX RX TX TX TX TX TX TX RX TX TX TX TX RX TX RX DATA (LSB FIRST) Reset Presence CCh 0Fh 26h 00h <2 data Bytes> Reset Presence CCh Aah 26h 00h 07h <2 data Bytes> Reset Presence CCh 55h 26h 00h 07h Reset Presence CCh F0h 00h 00h <128 Bytes (DS1992)> <512 Bytes (DS1993)> Reset Presence COMMENTS Reset pulse (480ms to 960ms) Presence pulse Issue skip ROM command Issue write scratchpad command TA1, beginning offset = 6 TA2, address = 0026h Write 2 Bytes of data to scratchpad Reset pulse Presence pulse Issue skip ROM command Issue read scratchpad command Read TA1, beginning offset = 6 Read TA2, address = 0026h Read E/S, ending offset = 7, flags = 0 Read scratchpad data and verify Reset pulse Presence pulse Issue skip ROM command Issue copy scratchpad command TA1 TA2 AUTHORIZATION CODE E/S Reset pulse Presence pulse Issue skip ROM command Issue read memory command TA1, beginning offset = 6 TA2, address = 0000h Read entire memory Reset pulse Presence pulse, done
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1-WIRE BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS199_ is a slave device. The bus master is typically a microcontroller or PC. For small configurations the 1-Wire communication signals can be generated under software control using a single port pin. For multisensor networks, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip (DS9097U series) are recommended. This simplifies the hardware design and frees the microprocessor from responding in real-time. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-wire bus must have opendrain or three-state outputs. The 1-Wire port of the DS199_ is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3kbps and requires a pullup resistor of approximately 5kW. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120ms, one or more of the devices on the bus may be reset.
Figure 8. HARDWARE CONFIGURATION
BUS MASTER VPUP RPU DS199X 1-Wire PORT
RX
DATA 5 A Typ. 100 W MOSFET
RX TX
TX Open Drain Port Pin
RX = RECEIVE TX = TRANSMIT
TRANSACTION SEQUENCE
The protocol for accessing the DS199_ through the 1-Wire port is as follows: Initialization ROM Function Command Memory Function Command Transaction/Data
INITIALIZATION
All transactions on the 1-wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
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slave(s). The presence pulse lets the bus master know that the DS199_ is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (see the flow chart in Figure 9).
Read ROM [33h]
This command allows the bus master to read the DS199_'s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if there is a single DS199_ on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number usually result in a mismatch of the CRC.
Match ROM [55h]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS199_ on a multidrop bus. Only the DS199_ that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64-bit ROM sequence wait for a reset pulse. This command can be used with single or multiple devices on the bus.
Skip ROM [CCh]
This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result).
Search ROM [F0h]
When a system is initially brought up, the bus master may not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify the ROM codes of the remaining devices. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example.
1-WIRE SIGNALING
The DS199_ require strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data. The bus master initiates all these signals except presence pulse. The initialization sequence required to begin any communication with the DS199_ is shown in Figure 10. A reset pulse followed by a presence pulse indicates the DS199_ is ready to send or receive data given the correct ROM command and memory function command. The bus master transmits (Tx) a reset pulse (tRSTL, minimum 480ms). The bus master then releases the line and goes into receive mode (Rx). The 1-Wire bus is pulled to a high state through the pullup resistor. After detecting the rising edge on the data line, the DS199_ waits (tPDH, 15ms to 60ms) and then transmits the presence pulse (tPDL, 60ms to 240ms).
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Figure 9. ROM FUNCTIONS FLOW CHART
M a s te r T X R es et P u ls e D S 1 9 9X T X P re s e nc e P u ls e M as te r T X R O M F u nc tio n C om m an d 33 H R e ad R O M C om m a n d ? Y N 5 5H M a tc h R O M C o m m a nd ? Y F 0H S ea rc h R O M C o m m an d ? Y N CCH S k ip R O M C o m m a nd ? Y N
N
D S 19 9X T X F am ily C o d e 1 B yte
D S 19 9 X T X B it 0 M a s ter T X B it 0 D S 19 9 X T X B it 0 M as te r T X B it 0 B it 0 M atc h ? Y N N B it 0 M atc h ? Y D S 19 9 X T X B it 1 M a s ter T X B it 1 D S 19 9 X T X B it 1 M as te r T X B it 1 B it 1 M atc h ? Y N N B it 1 M a tc h ? Y D S 19 9 X T X B it 6 3
D S 19 9X T X S e rial N um b er 6 B ytes
D S 19 9X T X C R C B yte
M a s ter T X B it 63
D S 19 9 X T X B it 6 3 M as te r T X B it 6 3
B it 63 M atc h ? Y
N
N
B it 6 3 M a tc h ? Y
M as te r T X M em ory F u nc tio n C om m an d
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Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSE
MASTER TX "RESET PULSE" VPULLUP VPULLUP MIN VIH MIN VIL MAX 0V tRSTL RESISTOR MASTER DS199X tR tPDH tPDL
* In order not to mask interrup signaling by other devices on the 10Wire bus tRSTL + tR should always be less than 960 us ** Includes recovery time
MASTER RX "PRESENCE PULSE" tRSTH
480 s tRSTL < * 480 s tRSTH < ** 15 s tPDH < 60 s 60 tPDL < 240 s
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 11. The master driving the data line low initiates all time slots. The falling edge of the data line synchronizes the DS199_ to the master by triggering a delay circuit in the DS199_. During write time slots, the delay circuit determines when the DS199_ samples the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit determines how long the DS199_ holds the data line low overriding the 1 generated by the master. If the data bit is a 1, the iButton leaves the read data time slot unchanged.
Figure 11. READ/WRITE TIMING DIAGRAM Write-One Time Slot
VPULLUP MIN VIH MIN VIL MAX 0V tLOW1 15s 60s tSLOT < 120 s 60 s 1 s tLOW1 < 15 s 1 s tREC < VPULLUP tSLOT tREC
DS199X Sampling Window
RESISTOR MASTER
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Figure 11. READ/WRITE TIMING DIAGRAM (continued) Write-Zero Time Slot
VPULLUP MIN VIH MIN VIL MAX 0V 15s 60s t LOW0 RESISTOR MASTER 60 s tLOW0 < tSLOT < 120 s 1 s tREC < VPULLUP tSLOT tREC
DS199X Sampling Window
Read-Data Time Slot
VPULLUP MIN VIH MIN VIL MAX 0V tSU tLOWR RESISTOR MASTER DS199X tRDV 1 s tREC < tRDV = 15 s tSU < 1 s Master Sampling Window VPULLUP tSLOT tREC
tRELEASE
60 s tSLOT < 120 s 1 s tLOWR < 15 s 0 tRELEASE < 45 s
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PHYSICAL SPECIFICATIONS
Size Weight Expected Service Life Safety See mechanical drawing 3.3 grams (F5 package) 10 years at +25C Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class I, Division 1, Group A, B, C and D Locations -0.5V to +7.0V -40C to +70C -40C to +70C
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground Operating Temperature Range Storage Temperature Range
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Logic 1 (Notes 1, 2) Logic 0 (Note 1) Output Logic Low at 4mA (Note 1) Output Logic High (Notes 1, 3) Input Load Current (Note 4) SYMBOL VIH VIL VOL VOH IL SYMBOL CIN/OUT SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL MIN MIN 2.2 -0.3
(VPUP = 2.8V to 6.0V; -40C to +70C.)
TYP MAX +0.8 0.4 VPUP 5 TYP 100 TYP MAX 800 MAX 120 15 120 45 1 UNITS V V V V mA
CAPACITANCE
PARAMETER I/O (1-Wire) (Notes 5, 6) PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Data Valid Release Time Read Data Setup (Note 7) Recovery Time Reset Time High (Note 8) Reset Time Low (Note 9) Presence Detect High Presence Detect Low
(TA = +25C)
UNITS pF UNITS ms ms ms ms ms ms ms ms ms ms ms
AC ELECTRICAL CHARACTERISTICS
MIN 60 1 60 0 1 480 480 15 60
(VPUP = 2.8V to 6.0V; -40C to +70C.)
exactly 15 15
960 60 240
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Note 1: All voltages are referenced to ground. Note 2: VIH is a function of the external pullup resistor and the VCC power supply. Note 3: VPUP = external pullup voltage. Note 4: Input load is to ground. Note 5: Capacitance on the data line could be 800pF when power is first applied. If a 5kW resistor is used to pull up the data line to VPUP, 5ms after power has been applied, the parasite capacitance does not affect normal communications. Note 6: Guaranteed by design, not production tested. Note 7: Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1ms of this falling edge, and remains valid for 14ms minimum. (15ms total from falling edge on 1-Wire bus.) Note 8: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 9: The reset low time (tRSTL) should be restricted to a maximum of 960ms, to allow interrupt signaling; otherwise it could mask or conceal interrupt pulses.
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